In the prior art U.S. Pat. to B. P. Ocshner No. 3,348,210 issued Oct. 17, 1967, a plurality of data processing units are connectable by a first switching network to a plurality of segments of permanent memory containing work program and to a permanent memory segment containing the administrative or task assignment routines. The last instruction of each work program points to the task assignment routine. The data processing units are also connectable by a second switching network to a plurality of writable operand memory segments containing data storage locations and, in the operand memory, the data processing units may access changeable task assignment words that contain pointers to the segments of the permanent memory containing programs to be executed. Each of the task assignment words contains a field (called an absolute enabling bit) to identify when that task word is active and a counter field (called conditional enabling bits) which is updated as each program is completed that must be executed as a prerequisite to making the task word active. When the counter field contains a full count, the absolute enabling bit makes the task word effective to designate that program in permanent memory which is next to be executed. The efficient functioning of the Ochsner arrangement thus requires the use of a segmented random access memory unit where each segment is dedicated to a particular program, a practice that is not efficient if the program is not frequently to be executed. If a particular memory segment becomes defective, that program can no longer be executed.
Further, while segmentation of the memory allows each of the Ochsner data processors to access a different memory segment, two data processors cannot simultaneously access the same memory segment. However, some real time control operations, such as digit collection in telephone switching applications may be required to be performed on a simultaneous basis so that two or more calls can be processed through the switching network at the same time. The Ochsner arrangement would require a number of duplicate memory segments to be dedicated equal to the maximum number of simultaneous calls that the system was designed to accommodate, even though, under light traffic conditions, less than all of such segments would be needed.
In addition to the Ochsner type of segmented memory system there are a number of other types of memory arrangements. In one of these arrangements a program segment called a page may be temporarily read from the main memory unit and written into a local cache memory unit. A cache memory unit is normally used only when the data processor's cycle time is less than the main memory unit's cycle time. The cache memory, which normally would have a faster overall access time than the main memory unit (perhaps 80-150 nanoseconds as compared to one microsecond for a 1 to 2 megabyte size memory unit), is particularly efficient in programming applications where the page of program will be repetitively exercised. Where the page is not repetitively used, the amount of time that the data processor must wait while the cache memory is being filled from the main memory may well counteract any savings in faster cache memory access time. Because practical considerations seem to rule out the requirement that the programmer must mark in advance those programs which should or should not be permitted to be paged into the cache memory at any instant of time, the likelihood of inefficient cache memory usage is present whenever an infrequently used program is paged into the cache memory. An example of prior art multiprocessor arrangement employing an individual cache memory permanently available to each data processing unit is shown in Parkin, U.S. Pat. No. 4,073,005, issued Feb. 7, 1978. In this arrangement any processor may page a desired program segment into its cache memory but must wait while the cache memory is being loaded before it can begin to execute the desired segment.
The recent past has seen great increases made in the intrinsic "power" of processor units. However, the use of high level programming languages has tended to offset the throughput benefit of the improvement in processor technology. Further, it would be advantageous to have a data processing arrangement where the processing power was not circumscribed by waiting time limitations.